Design of a high performance CNFET 10T SRAM cell at 5nm technology node

This article proposes a CNFET 10T SRAM cell based on Stanford Virtual Source model at 5nm technology node, through optimization design and simulation analysis to select optimum gate widths of transistors ensure best performance in terms stability, speed power consumption. We compare the proposed with optimized 6T [9]. It was found that timing characteristics is better than structure, static consumption greatly reduced while RSNM improved by 93.5%, read write EDP are 68.5% 96%, respectively.